Computer Science & Physics
I'm currently completing my final year at the University of Edinburgh studying Computer Science and Physics for my undergraduate degree.
Experience
Education
Skills
Designed a framework using approximate program synthesis (AppSyn) and syntax-guided synthesis (SyGuS) with CVC5 to generate and optimise arithmetic components for ML accelerators under MX (Microscaled) data formats. Integrated high-level synthesis (HLS) for Verilog generation and PPA evaluation.
Implemented the Arithmetic Logic Unit (ALU) and register file, iteratively optimising performance by buffering the multiplier and implementing data forwarding with stalling to prevent data hazards. Tested the processor’s performance on an FPGA board.
Copyright © 2026 Joseph Luke